As shown in Figure 3, the device allows reprogramming
of the DCO frequency up to ±3500 ppm from the center
frequency configuration without interruption to the
output clock. Changes greater than the ±3500 ppm
window will cause the device to recalibrate its internal
tuning circuitry, forcing the output clock to momentarily
stop and start at any arbitrary point during a clock cycle.
This re-calibration process establishes a new center
frequency and can take up to 10 ms. Circuitry receiving
a clock from the Si57x device that is sensitive to glitches
or runt pulses may have to be reset once the
recalibration process is complete.
So, it is in fact this recalibration process that establishes the new centre frequency. This has been verified by experimentation.
From this I conclude there is a small frequency change procedure and a large frequency change procedure. If the DCO frequency is changed no more than +/- 3500 ppm from the last centre frequency the a simple ratio multiplier is applied according to the following formulae:
Once a new RFREQ value (38 bits) is calculated, it is written to the Si570 device. Since several registers must be rewritten, even with tiny changes in the RFREQ value these changes can affect the DCO frequency while the set of registers are being updated. The Si570 provides a bit (register 135 bit 5) that can prevent this behaviour. Setting this bit to 1 before changing the RFREQ registers and then resetting it will allow the output frequency to change in a single phase continuous step to the new frequency.
When changing the DCO frequency by more than +/- 3500 ppm, several steps are involved. Firstly, new values must be calculated for the HSDIV and N1 divisors. Given the new desired output frequency, you must find the frequency divider values that will keep the DCO oscillation frequency in the range of 4.85 to 5.67 GHz.
To help minimize the device's power consumption, the divider values should be selected to keep the DCO's oscillation frequency as low as possible. The lowest value of N1 with the highest value of HS_DIV also results in the best power savings. Since there are many solutions for a given output frequency, it is useful for power sensitive applications to pay attention to these details.
Once the divisors have been calculated, a new RFREQ value is determined according to the following formulae:
The new values are written to the device as follows:
- Freeze the DCO by setting bit 4 of Register 137
- Write the new frequency configuration by setting RFREQ, HSDIV and N1 new values to the appropriate registers.
- Unfreeze the DCO and assert the NewFreq bit without exceeding the timeout specified in Table 11 of the Si570 datasheet. (Register 135, bit 6).
I find that the output waveform is basically a square wave signal. On my device at least there is a bit of overshoot on the square wave signal both positive and negative at least at lower frequencies. As I go higher in frequency, the waveform becomes more triangular in shape. I will post oscilloscope traces of this behaviour later as my scope is a bit tied up right at the moment with another project.
More to come...